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ltc 4300a-3 1 4300a3fa typical application features description level-shifting hot swappable 2- wire bus buffer with enable the lt c ? 4300a-3 hot swappable 2- wire bus buffer allows i/o card insertion into a live backplane without corruption of the data and clock busses. when the connection is made , the ltc4300a-3 provides bidirectional buffering, keeping the backplane and card capacitances isolated. rise time accelerator circuitry allows the use of weaker dc pull-up currents while still meeting rise time requirements. during insertion, the sda and scl lines are precharged to 1 v to minimize bus disturbances. the ltc4300 a -3 provides level translation between 3.3 v and 5 v supplies. the backplane and card can both be powered with supplies ranging from 2.7 v to 5.5 v. the ltc4300 a -3 also incorporates a cmos threshold enable pin which forces the part into a low current mode and isolates the card from the backplane. when driven to v cc , the enable pin sets normal operation. the ltc4300 a-3 is available in the msop and 3 mm 3 mm dfn packages. input?output connection applications n bidirectional buffer* for sda and scl lines increases fanout n prevents sda and scl corruption during live board insertion and removal from backplane n logic threshold enable input n isolates input sda and scl lines from output n compatible with i 2 c, i 2 c fast mode and smbus standards (up to 400khz operation) n 1 v precharge on all sda and scl lines n supports clock stretching, arbitration and synchronization 5 v to 3.3v level translation high impedance sda, scl pins for v cc = 0v, v cc2 = 0v small 8-lead dfn and msop packages n hot board insertion n servers n capacitance buffer/bus extender n desktop computer l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. *patent pending. v cc 3.3v 10k 10k enable sclin sclout sdain sdaout 5 4 6 7 3 2 8 1 gnd ltc4300a-3 0.01f 0.01f v cc2 4300a3 ta01 10k 10k off on 200ns/div output side 50pf 0.5v/div 4300a3 ta01b inputside 150pf downloaded from: http:///
ltc 4300a-3 2 4300a3fa pin configuration absolute maximum ratings v cc to gnd .................................................. C 0.3 v to 7v v cc 2 to gnd ................................................. C0.3 v to 7v sdain , sclin , sdaout , sclout ................ C0.3 v to 7v enable ........................................................ C0.3 v to 7v operating temperature range ltc 4300 a -3 c ......................................... 0 c to 70 c ltc 4300 a -3 i........................................ C40 c to 85 c (note 1) order information top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 9 4 3 2 1 v cc2 sclout sclin gnd v cc sdaoutsdain enable t jmax = 125c, ja = 43c/w exposed pad (pin 9), pcb connection is optional 12 3 4 v cc2 sclout sclin gnd 87 6 5 v cc sdaoutsdain enable top view ms8 package 8-lead plastic msop t jmax = 125c, ja = 200c/w storage temperature range msop ................................................ C65 c to 150 c dfn .................................................... C65 c to 125 c lead temperature ( soldering , 10 sec ) msop only ....................................................... 300 c lead free finish tape and reel part marking* package description temperature range ltc4300a-3cdd#pbf ltc4300a-3cdd#trpbf lbhg 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc4300a-3idd#pbf ltc4300a-3idd#trpbf lbhg 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc4300a-3cms8#pbf ltc4300a-3cms8#trpbf ltbhd 8-lead plastic msop 0c to 70c ltc4300a-3ims8#pbf lltc4300a-3ims8#trpbf ltbhf 8-lead plastic msop C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc 4300a-3 3 4300a3fa electrical characteristics symbol parameter conditions min typ max units power supplyv cc positive supply voltage l 2.7 5.5 v v cc2 card side supply voltage l 2.7 5.5 v i sd supply current in shutdown mode v enable = 0v 20 a i vcc1 v cc supply current v sdain = v sclin = 0v, v cc1 = v cc2 = 5.5v 3 4.1 ma i vcc2 v cc2 supply current v sdaout = v sclout = 0v, v cc1 = v cc2 = 5.5v 2.1 2.9 ma start-up circuitryv pre precharge voltage sda, scl floating l 0.8 1.0 1.2 v t idle bus idle time l 50 95 150 s v en enable threshold voltage 0.5 ? v cc 0.9 ? v cc v v dis disable threshold voltage enable pin 0.1 ? v cc 0.5 ? v cc v i en enable input current enable from 0v to v cc 0.1 1 a t phl enable delay, on-off 10 ns t plh enable delay, off-on 95 s rise time accelerators i pullupac transient boosted pull-up current positive transition on sda, scl, v cc = 2.7v, v cc2 = 2.7v, slew rate = 1.25v/s (note 2) 1 2 ma input-output connectionv os input-output offset voltage 10k to v cc on sda, scl, v cc = 3.3v (note 3), v cc2 = 3.3v, v in = 0.2v l 0 100 175 mv f scl, sda operating frequency guaranteed by design, not subject to test 0 400 khz c in digital input capacitance guaranteed by design, not subject to test 10 pf v ol output low voltage, input = 0v sda, scl pins, i sink = 3ma, v cc = 2.7v, v cc2 = 2.7v l 0 0.4 v i leak input leakage current sda, scl pins = v cc = 5.5v, v cc2 = 5.5v 5 a timing characteristics f i2c i 2 c operating frequency (note 4) 0 400 khz t buf bus free time between stop and start condition (note 4) 1.3 s t hd,sta hold time after (repeated) start condition (note 4) 0.6 s t su,sta repeated start condition setup time (note 4) 0.6 s t su,sto stop condition setup time (note 4) 0.6 s t hd, dat data hold time (note 4) 300 ns t su, dat data setup time (note 4) 100 ns t low clock low period (note 4) 1.3 s t high clock high period (note 4) 0.6 s t f clock, data fall time (notes 4, 5) 20 + 0.1 ? c b 300 ns t r clock, data rise time (notes 4, 5) 20 + 0.1 ? c b 300 ns t phl,skew high-to-low propagation delay skew, scl-sda v cc = 2.7v, v cc2 = 5.5v; v cc = 5.5v, v cc2 = 2.7v (note 6) l 0 75 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v cc2 = 2.7v to 5.5v, unless otherwise noted. downloaded from: http:///
ltc 4300a-3 4 4300a3fa C25 0 C50 25 50 75 100 temperature (c) i cc (ma) 4300a3 g01 5.35.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 v cc = 5.5v v cc = 2.7v C50 C25 0 25 50 75 100 temperature (c) t phl (ns) 4300a3 g02 100 8060 40 20 0 v cc = 2.7v v cc = 3.3v v cc = 5.5v c in = c out = 100pf r pullupin = r pullupout = 10k r pullup () 0 10,000 20,000 30,000 40,000 v out C v in (mv) 4300a3 g04 300250 200 150 100 50 0 v cc = 3.3v v cc = 5v t a = 25c v in = 0v temperature (c) C50 3530 25 20 15 10 50 25 75 4300a3 g05 C25 0 50 100 i sd (a) v cc = 5.5v v cc = 2.7v C50 C25 0 25 50 75 100 temperature (c) i pullupac (ma) 4300a3 g03 1210 86 4 2 0 v cc = 2.7v v cc = 5v v cc = 3v typical performance characteristics connection circuitry v out ? v in i sd vs temperature i cc vs temperature input?output high to low propagation delay vs temperature i pullupac vs temperature note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: i pullupac varies with temperature and v cc voltage, as shown in the typical performance characteristics section. note 3: the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pull-up resistor and v cc voltage is shown in the typical performance characteristics section. note 4: guaranteed by design, not subject to test. note 5: c b = total capacitance of one bus line in pf. note 6: these tests measure the difference in high-to-low propagation delay t phl between the clock and data channels. the delay on each channel is measured from the 50% point of the falling driven input signal to the 50% point of the output driven by the ltc4300a-3.the skew is defined as (t phl(scl) - t phl(sda) ). testing is performed in both directions from input bus to output bus and vice versa. tests are performed with approximately 500pf of distributed equivalent capacitance on each sda and scl pin. electrical characteristics downloaded from: http:///
ltc 4300a-3 5 4300a3fa pin functions v cc2 ( pin 1): card supply voltage. this is the supply voltage for the devices on the card i 2 c busses. connect pull-up resistors from sdaout and sclout to this pin. place a bypass capacitor of at least 0.01 f close to this pin for best results.sclout ( pin 2): serial clock output. connect this pin to the scl bus on the card. sclin ( pin 3): serial clock input. connect this pin to the scl bus on the backplane. gnd ( pin 4): device ground. connect this pin to a ground plane for best results.enable ( pin 5): digital cmos threshold input. ground- ing this pin puts the part in a low current mode. it also disables the rise time accelerators, disables the bus discharge circuitry, isolates sdain from sdout and isolates sclin from sclout. for active operation, drive this pin to v cc . if this feature is unused, tie to v cc . since enable is v cc referenced, do not connect to v cc2 or pull up to v cc2 . sdain ( pin 6): serial data input. connect this pin to the sda bus on the backplane. sdaout ( pin 7): serial data output. connect this pin to the sda bus on the card. v cc ( pin 8): main input power supply from backplane. this is the supply voltage for the devices on the backplane i 2 c busses. connect pull-up resistors from sdain and sclin to this pin. place a bypass capacitor of at least 0.01f close to this pin for best results. exposed pad ( pin 9, dfn package only): exposed pad may by be left open or connected to device ground. (dfn/msop) downloaded from: http:///
ltc 4300a-3 6 4300a3fa block diagram 100k 100k C + C + 0.5pf 3 sclin enable uvlo 4300a3 bd connect connect stop bit and bus idle 4 4 gnd 20pf rds qb 0.5a 0.55v cc / 0.45v cc C + C + v cc2 C 1v 2ma backplane-to-card connection connect connect 2 sclout 6 sdain 8 v cc backplane-to-card connection connect connect 7 sdaout 1 v cc2 1v precharge 100k 100k connect slew rate detector 2ma slew rate detector 2ma slew rate detector 2ma slew rate detector 95s delay, rising only 5 2-wire bus buffer and hot swap ? controller downloaded from: http:///
ltc 4300a-3 7 4300a3fa operation start-up when the ltc4300a-3 first receives power on its v cc pin, either during power-up or during live insertion, it starts in an undervoltage lockout ( uvlo) state, ignoring any activity on the sda and scl pins until v cc rises above 2.5v. the part also waits for v cc2 to rise above 2 v. this ensures that the part does not try to function until it has enough voltage to do so.during this time, the 1 v precharge circuitry is also ac - tive and forces 1 v through 100 k nominal resistors to the sda and scl pins. because the i/o card is being plugged into a live backplane, the voltage on the backplane sda and scl busses may be anywhere between 0 v and v cc . precharging the scl and sda pins to 1 v minimizes the worst - case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the i/o card. once the ltc4300a-3 comes out of uvlo, it assumes that sdain and sclin have been inserted into a live system and that sdaout and sclout are being powered up at the same time as itself. therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. when either one occurs, the part also verifies that both the sdaout and sclout voltages are high. when all of these conditions are met, the input - to - output connection circuitry is activated, joining the sda and scl busses on the i/o card with those on the backplane, and the rise time accelerators are enabled. connection circuitry once the connection circuitry is activated, the functionality of the sdain and sdaout pins is identical. a low forced on either pin at any time results in both pin voltages being low. for proper operation, logic low input voltages should be no higher than 0.4 v with respect to the ground pin voltage of the ltc4300a-3. sdain and sdaout enter a logic high state only when all devices on both sdain and sdaout release high. the same is true for sclin and sclout . this important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the ltc4300a-3. another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. input to output offset voltage when a logic low voltage, v low1 , is driven on any of the ltc4300a-3s data or clock pins, the ltc4300a-3 regulates the voltage on the other side of the part ( call it v low2 ) to a slightly higher voltage, as directed by the following equation (typical): v low2 = v low1 + 75mv + (v cc /r ) ? 70 [] where r is the bus pull-up resistance in ohms. for ex- ample, if a device is forcing sdaout to 10 mv where v cc = 3.3 v and the pull-up resistor r on sdain is 10 k, then the voltage on sdain = 10 mv + 75 mv + (3.3/10000) ? 70 = 108 mv ( typical). see the typical performance char- acteristics section for curves showing the offset voltage as a function of v cc and r. propagation delaysduring a rising edge, the rise time on each side is determined by the combined pull-up current of the ltc4300a-3 boost current and the bus resistor and the equivalent capacitance on the line. if the pull-up currents are the same, a differ- ence in rise time occurs which is directly proportional to the difference in capacitance between the two sides. this effect is displayed in figure 1 for v cc = v cc2 = 3.3 v and a 10 k pull-up resistor on each side (50 pf on one side and 150 pf on the other). since the output side has less capacitance than the input, it rises faster and the effective propagation delay is negative. there is a finite propagation delay through the connection circuitry for falling waveforms. figure 2 shows the falling edge waveforms for the same v cc , pull-up resistors and equivalent capacitance conditions as used in figure? 1. an external nmos device pulls down the voltage on the side with 150 pf capacitance; the ltc4300a-3 pulls down the voltage on the opposite side, with a delay of 55ns. this delay is always positive and is a function of downloaded from: http:///
ltc 4300a-3 8 4300a3fa supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. the typical performance characteristics section shows t phl as a function of temperature and voltage for 10 k pull-up resistors and 100 pf equivalent capacitance on both sides of the part. by comparison with figure 2, the v cc = v cc2 = 3.3 v curve shows that increasing the capacitance from 50pf to 100 pf results in a propagation delay increase from 55ns to 75ns. larger output capacitances translate to longer delays ( up to 150 ns). users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. rise time accelerators once connection has been established, rise time accelerator circuits on all four sda and scl pins are activated. these allow the user to choose weaker dc pull-up currents on the bus, reducing power consumption while still meet- ing system rise time requirements. during positive bus transitions, the ltc4300a-3 switches in 2 ma ( typical) of current to quickly slew the sda and scl lines once their dc voltages exceed 0.6 v. using a general rule of 20 pf of capacitance for every device on the bus (10 pf f or the device and 10 pf for interconnect), choose a pull - up current so that the bus will rise on its own at a rate of at least 1.25 v/s to guarantee activation of the accelerators. for example, assume an smbus system with v cc = 3 v, a 10 k pull-up resistor and equivalent bus capacitance of 200pf. the rise time of an smbus system is calculated from ( v il(max) C 0.15 v) to ( v ih(min) + 0.15 v), or 0.65 v to 2.25 v. it takes an rc circuit 0.92 time constants to traverse this voltage for a 3 v supply; in this case , 0.92 ? (10 k ? 200 pf ) = 1.84 s. thus, the system exceeds the maximum allowed rise time of 1 s by 84%. however, using the rise time accelerators, which are activated at a dc threshold of below 0.65 v, the worst-case rise time is: (2.25v C 0.65 v ) ? 200 pf/1ma = 320 ns, which meets the 1s rise time requirement.enable low current disable grounding the enable pin disconnects the backplane side from the card side, disables the rise time accelerators, disables the bus precharge circuitry and puts the part in a near-zero current state. when the pin voltage is driven all the way to v cc , the part waits for data transactions on both the backplane and card sides to be complete ( as described in the start-up section) before reconnecting the two sides. figure 1. input?output connection low to high transition figure 2. input?output connection high to low transition 200ns/div output side 50pf 0.5v/div 4300a3 f01 inputside 150pf 200ns/div input side 150pf 0.5v/div 4300a3 f02 outputside 50pf downloaded from: http:///
ltc 4300a-3 9 4300a3fa resistor pull-up value selection the system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 v/s on the sda and scl pins, in order to activate the boost pull-up currents during rising edges. choose maximum resistor value r using the formula: r (v cc(min) C 0.6)(800,000)/c where r is the pull-up resistor value in ohms, v cc(min) is the minimum v cc voltage and c is the equivalent bus capacitance in picofarads (pf). in addition, regardless of the bus capacitance, always choose r 16 k for v cc = 5.5 v maximum, r 24 k for v cc ? =? 3.6v maximum. the start-up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. applications information figure 3. the ltc4300a-3 in a pci application where all the pins have the same length. enable should be held low until all transients associated with the live insertion have settled live insertion and capacitance buffering application figures 3 and 4 illustrate the usage of the ltc4300a-3 in applications that take advantage of both its hot swap controlling and capacitance buffering features. in all of these applications, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise - and fall time requirements difficult to meet. placing a ltc4300a-3 on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the ltc4300 a -3 drives the capacitance of every - thing on the card and the backplane must drive only the capacitance of the ltc4300a-3, which is less than 10 pf. v cc sdain sclin v cc2 gnd sdaout sclout enable 4300a3 f03 r210k r3 10k r110k r4 10k r510k r6 10k i/o peripheral card 1 ltc4300a-3 c2 0.01f card_scl card_sda r7 10k r8 10k v cc2 backplane backplane connector sda scl ena2 ena1 v cc c1 0.01f v cc sdain sclin v cc2 gnd sdaout sclout enable i/o peripheral card 2 ltc4300a-3 c4 0.01f card2_scl card2_sda c3 0.01f downloaded from: http:///
ltc 4300a-3 10 4300a3fa 5v to 3.3v level translator and power supply redundancy systems requiring different supply voltages for the back- plane side and the card side can use the ltc4300a-3, as shown in figure 5. the pull-up resistors on the card side connect from sdaout to sclout to v cc2 , and those on the backplane side connect from sdain and sclin to v cc . the ltc4300a-3 functions for voltages ranging from 2.7 v to 5.5 v on both v cc and v cc2 . there is no constraint on the voltage magnitudes of v cc and v cc2 with respect to each other. this application also provides power supply redundancy. if the v cc2 voltage falls below its uvlo threshold, the ltc4300a-3 disconnects the backplane from the card, so that the backplane can continue to function. if the v cc voltage falls below its uvlo threshold and the v cc2 voltage remains active, hold enable at ground to ensure proper operation. applications information figure 4. the ltc4300a-3 in a custom application. making enable the shortest pin ensures that v cc and v cc2 connect before enable is allowed to go high, connecting the card to the backplane v cc sdain sclin v cc2 gnd sdaout sclout enable 4300a-3 f04 i/o peripheral card 1 ltc4300a-3 c2 0.01f card_scl card_sda r7 10k r8 10k v cc2 backplane backplane connector sda scl ena2 ena1 v cc c1 0.01f v cc sdain sclin v cc2 gnd sdaout sclout enable i/o peripheral card 2 ltc4300a-3 c4 0.01f card2_scl card2_sda c3 0.01f staggered connector staggered connector r110k r210k r3 10k r410k r510k r6 10k downloaded from: http:///
ltc 4300a-3 11 4300a3fa package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) note:1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50bsc 0.70 0.05 3.5 0.05 packageoutline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) downloaded from: http:///
ltc 4300a-3 12 4300a3fa msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 C 6 typ detail a detail a gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. downloaded from: http:///
ltc 4300a-3 13 4300a3fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 09/12 updated format of pin configuration and order information sections 2 added t phl,skew parameter to electrical characteristics 3 downloaded from: http:///
ltc 4300a-3 14 4300a3fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0912 rev a ? printed in usa related parts typical application part number description comments ltc1380/ltc1393 single-ended 8-channel/differential 4-channel analog mux with smbus interface low r on : 35 single-ended /70 differential, expandable to 32 single or 16 differential channels ltc1427-50 micropower, 10-bit current output dac with smbus interface precision 50a 2.5% tolerance over temperature, 4 selectable smbus addresses, dac powers up at zero or mid-scale ltc1623 dual high side switch controller with smbus interface 8 selectable addresses/16-channel capability ltc1663 smbus interface 10-bit rail-to-rail micropower dac dnl < 0.75lsb max, 5-lead sot-23 package ltc1694/ltc1694-1 smbus accelerator improved smbus/i 2 c rise time, ensures data integrity with multiple smbus/i 2 c devices lt1786f smbus controlled ccfl switching regulator 1.25a, 200khz, floating or grounded lamp configurations ltc1695 smbus/i 2 c fan speed controller in thinsot? 0.75 pmos 180ma regulator, 6-bit dac ltc1840 dual i 2 c fan speed controller tw o 100a 8-bit dacs, tw o tach inputs, four gpi0 ltc4300a-1/ltc4300a-2 hot swappable 2-wire bus buffer preserves data integrity under hot swap conditions, provides capacitive buffering, rise time acceleration ltc4301 supply independent 2-wire bus buffer provides capacitive buffer, 3.3v to 5v level translation with only the card bus v cc supply ltc4301l hot-swappable 2-wire bus buffer with low voltage level translation level translators, 1v signals to standard 3.3v and 5v logic rails ltc4302-1/ltc4302-2 addressable i 2 c and smbus compatible bus buffers provides capacitive buffering, rise time acceleration, and input to output connection control using 2-wire bus commands figure 5. 5v to 3.3v level translator v cc2 gnd sdaout sclout sdainsclin enable v cc r210k r310k card_v cc , 3.3v card_scl card_sda c2 0.01f c1 0.01f r110k v cc 5v r410k ltc4300a-3 scl sda 4300a-3 f05 downloaded from: http:///

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